Currently, one of the major bottlenecks in digital design is synthesis. Synthesis is tedious and time consuming, especially during the timing/power closure cycle. Each iteration of relatively small changes in a design takes several hours to synthesize, putting pressure on designers to carefully consider when to submit jobs and wait for the delayed feedback. This delay is especially problematic in FPGA emulation, when synthesis is performed frequently while fixing the system functionality.
Triggering synthesis over the whole design is currently widely adopted in industry and academia alike. Nevertheless, usually, at a given iteration, a designer is focusing on one small portion of the circuit. In traditional synthesis, even if a small portion of the design is changed, logic synthesis and placement are triggered for large blocks and require hours to complete. This is due to two main reasons: tools are not designed for incremental synthesis, and inter-module optimization has a significant impact in QoR.
Recent research in incremental synthesis has proposed various approaches to incremental synthesis. One approach, for example, partitions the design into regions that are synthesized independently. After a change, only the partition is re-synthesized. The partitioning, however, is somewhat artificial. Consequently, there is a significant hit on QoR depending on the parameters choice. Since a single set of parameters is not applicable to any design, the utility of this approach is limited.
Even though the EDA industry has been trying to address the problem of long synthesis times, the current standards are either not fast enough or depend on manual interactions that often degrade design quality.